Method and apparatus for performing a multiple-input optical arithmetic comparison

ABSTRACT

An optical arithmetic comparator (OAC) is disclosed which is capable of comparing multiple numbers simultaneously, and indicating the common value of the multiple numbers being compared if the numbers are equal. The OAC includes at least two input channels each having a plurality of sources arranged in an identical pattern, the sources being capable of selective activation such that only one source is activated at a time within each of the channels to form a specific spatial light pattern, and a detector array which determines if the specific spatial light pattern indicated the numbers being compared are equal.

This application is a continuation of application Ser. No. 07/539,219, filed Jun. 18, 1990, now abandoned, which is a division of 07/287,275, filed Dec. 21, 1988, now abandoned.

BACKGROUND OF THE INVENTION

The present invention is related to an optical arithmetic comparator, and more specifically, to an optical comparator and method for comparing multiple digits simultaneously and displaying their common value.

A common task that arises in computing is to show that two or more numbers are equal. A comparison operation of only two numbers can be accomplished by showing that their difference is zero. When more than two numbers are to be compared, however, the method usually utilized is to compare the numbers in pairs and then show that all the pairs are equal via a logical tree.

The above described comparison of more than two numbers takes more than one process step to complete, even in parallel logic, thereby delaying the comparison operation. In addition, the comparison operation is further delayed in conventional electronic computing systems in which the speed is inherently limited by the RC time constants of the interconnecting wiring.

Recent progress in the field of optical computing has led to the demand for optical components, such as optical comparators, capable of overcoming the inherent speed limitations of conventional electronic computing systems. For example, U.S. Pat. No. 4,604,707 issued to Yamashita et al discloses an optical comparator that compares two binary input light patterns. The light patterns are scanned serially by an acoustic wave device in order to effect a bit-by-bit comparison of the input patterns. While providing some advantages over conventional electronic comparators, the speed of the disclosed optical comparator is limited to the speed limitations of the acoustic wave device and still requires multiple comparisons of bit pairs.

SUMMARY OF THE INVENTION

The present invention overcomes the disadvantages and limitations discussed above by providing an optical arithmetic comparator and method for comparing multiple numbers simultaneously. In addition, the optical arithmetic comparator of the present invention is capable of transmitting the common value of the multiple numbers being compared if the numbers are equal.

More specifically, in one preferred embodiment, the invention provides an optical comparator including at least two input channels each having a plurality of sources arranged in an identical pattern, the sources being capable of selective activation such that only one source is activated at a time within each of the channels to form a specific spatial light pattern, and a detector array having a plurality of detectors optically coupled to the plurality of sources via a light transfer system, the plurality of detectors of the detector array being adapted to detect when sources corresponding in pattern location in each input channel are activated simultaneously and to generate an output signal indicative thereof.

In another preferred embodiment, the invention provides an optical comparator including a plurality of input channels each including a plurality of independently controllable light sources arranged in an identical pattern, and a detector array having a plurality of detectors corresponding and optically coupled to the input channels via a light transfer system, the detectors of the detector array being adapted to detect when all of the sources in their corresponding input channel are activated simultaneously and to generate an output signal indicative thereof.

The present invention is particularly applicable to computing systems employing residue arithmetic. Briefly, residue arithmetic does not employ a "carry" operation, that is, each "digit" in the representation is independent of the other. Thus, for example, addition in residue arithmetic of corresponding "digit" in two numbers can effectively be carried out by a device that is not connected to other "digit", but parallel to other digits. In residue arithmetic, each "digit" in a representation of a number is the decimal value of the number modulo the prime number corresponding to that position, called the "modulus". Addition is the sum of corresponding representations of the number modulo the modulus. FIG. 1 gives examples of residue arithmetic in a "235" representation where 2 is the prime number associated with the left-most modulus, 3 with the central modulus, and 5 with the right-most modulus. Further information concerning residue arithmetic may be found in the text by Szabo and Tanaka entitled, Residue Arithmetic and Its Applications to Computer Technology, McGraw-Hill Book Company, New York, 1967.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference should be made to the following figures for a detailed understanding of residue arithmetic discussed above and the preferred embodiments of the invention in which:

FIG. 1 is a table of examples of residue arithmetic in a "235" representation;

FIG. 2 illustrates a first embodiment of the present invention employing pattern recognition using a digit-grouping technique;

FIG. 3 illustrates a second embodiment of the present invention employing pattern recognition using a value-grouping technique;

FIG. 4 illustrates a third embodiment of the present invention employing optical interconnection using the digit-grouping technique of FIG. 2;

FIG. 5 illustrates a fourth embodiment of the present invention employing optical interconnection using the value-grouping technique of FIG. 3;

FIGS. 6a and 6b illustrate an electrical and electro-optical complementary output circuit, respectively, that may be employed in the embodiments illustrated in FIGS. 2-5;

FIG. 7 illustrates a multi-input, opto-electronic AND circuit using photoconductive detectors that may be employed as a detector in the embodiments illustrated in FIGS. 2-5;

FIG. 8 illustrates a fifth embodiment of the present invention which includes an opto-electronic AND gate; and

FIG. 9 illustrates an enhancement of the multi-input, opto-electronic AND circuit illustrated in FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the invention will be described with reference to optical arithmetic comparators (OAC) for use in computing systems employing residue arithmetic but is not limited thereto.

Referring now to FIG. 2, a first embodiment of an optical arithmetic comparator according to the present invention is shown including a pattern recognition system employing a "digit-grouping" technique. A plurality of sources 10, which are preferably mutually coherent sources with the same phase and intensity, are provided in a spaced relationship along a plane A. The plurality of sources 10 are grouped into N input channels, where N is the number of digits to be compared, the sources within each input channel being equally spaced by the same distance D1. For example, three input channels (1, 2, 3) representing three digits to be compared are illustrated in FIG. 2. Each of the N digits to be compared is represented in a "one-of-m" format by the grouped sources 10 in each input channel. In the "one-of-m" format, one and only one of the m sources 10 for each input channel is active at a time. The order of the sources from 0 to m-1 is in the same direction (spatial orientation) for each input channel. Thus, the energization of the (m-3) light source 10 for each channel corresponds to the value "2" in each channel. FIG. 2, for example, shows the N=3, m=5 case for three input digits of modulus 5, e.g., N=3, m=5.

The distance D2 from the m-1 source of one input channel to the zero source of the next input can be different from the uniform spacing D1 between the sources in each input channel, but the distance D3 between sources corresponding in pattern location must be uniform. Thus, if the input digits have the same value, the active sources representing the input digits are uniformly spaced at distance D3 between channels for every input value. Recognition of a pattern of equally spaced active sources is determinative of equality of the input digits.

Light from each active source is passed through a Fourier Transform lens 12, having a focal length F and placed one focal length from the sources 10. A Fraunhofer interference pattern is formed on the other side of lens 12 at a distance F therefrom where a filter 14 is positioned. The filter 14 is made to match the interference pattern formed when the input digits are equal, i.e., when activated sources in each channel are equally spaced, in which case the resulting Fraunhofer diffraction pattern is related to a multiple slit interference pattern. Light emerging from the filter 14 passes through a second Fourier Transform lens 16, also having a focal length F and positioned a distance F downstream of filter 14. Light from lens 16 is focussed onto a detector array 18 positioned a distance F downstream of lens 16. Detector array 18 has m detectors 20 and m corresponding threshold circuits 22. The detectors are positioned at a distance of 4F from the plurality of sources 10.

The focused light forms a bright central spot with 2N spots of lesser intensity on either side of the central spot. If the input digits are equal, and if the brightness of each active input source is unity, then the central spot has a brightness proportional to N². The two nearest spots have brightness proportional to (N-1)², the next nearest proportional to (N-2)², and so on to zero brightness.

Each detector 20 (0 to (m-1)) of the detector array 18 is placed at the central spot of the pattern generated by correspondingly valued sources 10 (0 to (m-1)). As shown in FIG. 2, for example, the three input digits each have the value 4 such that the m-1 sources of each channel are activated. The (m-1) detector 20 is placed at the central spot of the pattern generated by the activated (m-1) sources 10 and the corresponding (m-1) threshold circuit 22 generates an output signal which not only indicates that the three input digits are equal, but is indicative of the value (4) of the three input digits.

If one of the input digits is different from the rest, the central spot has a brightness proportional to (N-1)². Hence, to detect equality of the input digits, the detectors 20 and their associated threshold circuits 22 must be capable of discriminating between signals proportional to (N-1)² and N² respectively. The threshold circuit output lines are kept separate if the common value (if any) of the digits is wanted. Otherwise, the threshold circuit output lines may be logically OR-ed together (not shown) to form a common "equality" output.

A second embodiment of the optical arithmetic comparator (OAC) is shown in FIG. 3. As in the first embodiment, each of the N digits to be compared in represented in "one-of-m" format by sources 10 arranged along a straight line. However, the sources 10 are grouped by input value, forming m "value-groups" or channels (0, 1, 2, 3, 4) of N elements each. The sources 10 are uniformly spaced a distance D4 within each channel and the N input digits occur in the same order. FIG. 3 illustrates the N=3, m=5 case for three input digits of modulus 5. If the three input digits are the same, the active sources representing them are all in the same channel with uniform spacing between them.

As in the first embodiment, the sources 10 are viewed with a Fourier optics arrangement of two lenses 12 and 16, a filter 14 and a detector array 18 each spaced apart by the focal lens F. If the spacing between the sources 10 of each channel is uniform, the Fraunhofer interference pattern from the activated sources of each channel will have the same size and hence the same matched filter can be used for detecting equal input values in all channels. The filter output light is focused in the detector plane in the same way as for the first embodiment, and the threshold for detecting equality lies between N² and (N-1)² as above.

The second embodiment has two advantages over the first. The Fraunhofer interference has a larger spatial period because the lights which are lit when the input digits are equal are closer together, and the distance between the detectors is also larger because the pattern of illuminated lights shifts more when the common value of the input digits is changed. These factors make aligning the matched filter and the detectors easier, making this embodiment somewhat more practical than the first.

However, the second embodiment has a peculiar property. If all the sources 10 are uniformly spaced, i.e. D4=D5, then some inputs other than the desired "all inputs equal" will have an output proportional to N² which is focussed at locations in between the "all inputs equal" detector locations. This may be illustrated for the case of three inputs of three values each. If these inputs are arranged in the pattern 222111000 with uniform spacing, then any pattern of three consecutive active sources will have the same spacing and will give the same brightness in the detector plane. In the case presented above, the patterns 222, 221, 211, 111, 110, 100, 000, are equally spaced whereas only 222, 111, 000 represent equal input digits. This property may be eliminated by making the spacing between channels (D5) different from the spacing of the sources within the channels (D4).

Third and fourth embodiments of the present invention are illustrated in FIGS. 4 and 5. In both embodiments, an optical interconnect structure 24 is used in place of the Fourier optics arrangements in the first and second embodiments. The interconnect structure from the sources 10 to the detectors 20, plus the following threshold circuits 22, form an optical analog of an electronic multiple input AND circuit.

Referring to FIG. 4., the third optical interconnect embodiment of an OAC according to the present invention uses the same pattern of sources as the first pattern recognition embodiment above, namely, digit-grouping. The optical interconnections 24 distribute unit amounts of energy from each active source to the appropriate detector 20 and may take the form of optical fibers or optical waveguides formed on substrates. (See for example, MacDonald et al "Hybrid Optoelectronic Integrated Circuit", Applied Optics, Vol. 26, No. 5, March 1987.) There is one detector 20 for each output value. The interconnect system has enough bound modes to preclude exciting radiation modes with the sources.

If the sources 10 are mutually coherent and have the same intensity, then the same relative brightness levels are found as in the pattern recognition embodiments above. However, incoherent light may be used instead, simplifying the structure of the sources 10. In this case, the light intensities at the detectors 20 are proportional to N when the input digits are equal, proportional to N-1 when one digit is different from the others, and so on down to 0. The detector threshold for detecting equal input digits is set between N and N-1, a tighter specification than when coherent light is used. The possibility of using incoherent light and dispensing with Fourier optics and the matched filter makes this embodiment, in some respects, more compact and commercially practical than the pattern recognition embodiments shown in FIGS. 3 and 4.

The fourth optical interconnect embodiment of the OAC shown in FIG. 5, uses the same pattern of sources as the second pattern recognition embodiment above, namely, value-grouping. The interconnect system here involves no crossovers of one path by another, and therefore could be made from light-tight baffles 26 to prevent light from one channel from reaching the detectors 20 associated with another channel. In cases where the sources 10 can be placed directly on the detector input aperture, and the detector uniformity is good enough to provide reliable discrimination between N active sources and N-1 active sources, then a system requiring minimal components can be constructed.

Most of the possible OAC input patterns will not activate any OAC output signal, and it may be desirable in some computing systems to provide a "no equality" signal. Two possible means for doing this are illustrated in FIGS. 6a and 6b. First, the outputs of the threshold circuits in each of the above embodiments are logically OR'ed together. The resulting common signal is applied to a complementing device 26 which provides two outputs, "equality" and "no equality". An electronic complementer is illustrated in FIG. 6a and may include, for example, a TTL SN74265. An electro-optic complementer is illustrated in FIG. 6b as an optical X-crossing switch 28 driven by the OR'ed signals. A discussion of x-crossing switches is provided by Neyer et al in the article entitled, "A Beam Propagation Method Analysis of Active and Passing Waveguide Crossings", Journal of Liqhtwave Technology, Vol. LT-3, No. 3, June 1985, the contents of which are hereby incorporated by reference.

The OAC according to the present invention is capable of providing functions other than direct comparison on digits. It can also be used to detect fixed patterns or equalities, for example, in the form x=y+a=z+b by symbolic substitution. The clearest illustration of this is in the "value-grouping" embodiment of the OAC illustrated in FIG. 5, wherein for a=1 and b=2, the input values (sources) are labeled 012₋₋ 123₋₋ 234₋₋ 340₋₋ 401 (modulus 5 arithmetic). Further, the equalities of the form x=ay=bz can also be handled by symbolic substitution. For a=2 and b=3, the input sources would be labeled xyz=000₋₋ 123₋₋ 241₋₋ 314₋₋ 432 (modulus 5 arithmetic). Equalities of these two forms combined can also be handled by a similar method.

The OAC is also capable of providing dual functions, as each detector and threshold circuit combination of the optical interconnect OAC embodiments illustrated in FIGS. 5 and 6 form an optical AND gate, which can be operated by binary input logic on the light sources. Each value-group then becomes a logical criterion to be satisfied with an AND event for these sources. Further, one may convert the AND operation to a MAJORITY operation by providing variable threshold circuits and suitably reducing the discrimination threshold. The threshold circuit outputs may still be OR'ed as before. Therefore, the OAC may be used as a general optical AND (or MAJORITY) gate system.

An alternate embodiment for each of the detectors 20 and their corresponding threshold circuits 22, illustrated in FIG. 4 for example, is to utilize a multiple-input, opto-electronic AND gate configuration 40-N as shown in FIG. 7, wherein photoconductive detectors 30-1 through 30-N are connected in series. A load resistor R_(L) is connected between detector 30-N and ground, and an output terminal 32 is provided between detector 30-N and load resistor R_(L). The opto-electronic AND gate configuration 40-N shown in FIG. 7 replaces, for example, each detector 20 and threshold circuit 22 pair shown in FIG. 4, as illustrated in FIG. 8. The output lines of the opto-electronic AND gates are OR'ed together by OR circuit 42 to form a common output line 43.

The operation of circuit illustrated in FIG. 7 may be considered first in reference to a simple case where N=2. If each detector 30-1 and 30-2 is operated away from saturation, then the resistance can be modeled by ##EQU1## where R_(i) is the detector resistance of detector 30i, α is a parameter with typical value of 100 ohmswatt, P_(D) is a dark power (relating to the detector dark current) with typical value of 10⁻⁷ watts and P_(I) is the input power. The voltage across the load resistor R_(L) is therefore given by

    V.sub.o =V.sub.B R.sub.L /(R.sub.L +R.sub.1 +R.sub.2)      (2)

If the load resistor RL is chosen so that when light is present on none or only one of the detectors, the condition ##EQU2## is true, and when both detectors are illuminated the condition ##EQU3## is true, then the output voltage will be zero and the bias voltage respectively. Thus, the circuit operates as an AND gate. For the applications of interest, both inputs are of equal value and may be scaled together in magnitude so that conditions 3 and 4 can always be met. For the multi-input AND gate shown in FIG. 7, conditions 3 and 4 become ##EQU4##

For additional gain enhancement, a variation of the circuit of FIG. 7 for two detectors using FETs is illustrated in FIG. 9. The operation of this circuit relies on the variable resistance of the FETs with input voltage and is otherwise similar to the circuit described in FIG. 7. The circuit illustrated in FIG. 9 may be straightforwardly extended for multi-inputs as with the circuit illustrated in FIG. 7. Other variations on both circuits are possible, with the basic operation relying on multiple series resistances that vary with input illumination.

While the invention has been described with reference to preferred embodiments, it is understood that various modifications and improvements may be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. 

What is claimed is:
 1. An optical comparator comprising:a) at least two input channels each having a plurality of non-coherent sources arranged in corresponding identical patterns, said non-coherent sources being capable of selective activation such that only one source is activated at a time within each of said channels to form a specific spatial light pattern; and b) a detector array having a plurality of detectors optically coupled to said plurality of non-coherent sources via a light transfer system, for detecting when non-coherent sources corresponding in pattern location in each input channel are activated simultaneously and for generating an output signal indicative thereof; wherein each of said input channels corresponds to a digit to be compared and each of said plurality of non-coherent sources within each of said input channels corresponds to the value of said digit; and wherein each of said detectors includes an output line; the output lines of said detectors are OR'ed together to form a common output line, and each of said detectors comprises an opto-electronic AND gate.
 2. An optical comparator as claimed in claim 1, wherein said opto-electronic AND gate comprises a plurality of photoconductive detectors connected in series between a voltage source and an output terminal.
 3. An optical comparator as claimed in claim 2 further including a load resistor connected between said output terminal and ground.
 4. An optical comparator comprising:a) at least two input channels each having a plurality of sources arranged in corresponding identical patterns, said sources being capable of selective activation such that only one source is activated at a time within each of said channels to form a specific spatial light pattern; and b) a detector array having a plurality of detectors optically coupled to said plurality of sources via a light transfer system, for detecting when sources corresponding in pattern location in each input channel are activated simultaneously and for generating an output signal indicative thereof; wherein each of said input channels corresponds to a digit to be compared and each of said plurality of sources within each of said input channels corresponds to the value of said digit; and wherein each of said detectors includes an output line; the output lines of said detectors are OR'ed together to form a common output line, and each of said detectors comprises an opto-electronic AND gate; and wherein said opto-electronic AND gate comprises a plurality of FET's connected in series between a voltage source and an output terminal, and wherein each gate electrode of said plurality of FET's is coupled to one of a plurality of input circuits.
 5. An optical comparator as claimed in claim 4 further including a load resistor connected between said output terminal and ground.
 6. An optical comparator as claimed in claim 4, wherein each input circuit comprises a series connection of a diode bias voltage source, a diode, a resistor, and ground, respectively, and wherein said gate electrodes are connected to an anode of said diode associated with said corresponding one of said input circuits.
 7. An optical comparator comprising:a) a plurality of input channels each including a plurality of independently controllable non-coherent light sources arranged in an identical pattern; and b) a detector array having a plurality of detectors corresponding and optically coupled to said input channels via a light transfer system, for detecting when all non-coherent light sources corresponding in the corresponding input channel are activated simultaneously and for generating an output signal indicative thereof; wherein each of said input channels corresponds to a digit to be compared and each of said plurality of non-coherent light sources within each of said input channels corresponds to the value of said digit; and wherein each of said detectors includes an output line, the output line of said detectors being OR'ed together to form a common output line, each of said detectors comprising an opto-electronic AND gate.
 8. An optical comparator as claimed in claim 7, wherein said opto-electronic AND gate comprises a plurality of photoconductive detectors connected in series between a voltage source and an output terminal ground, respectively.
 9. An optical comparator as claimed in claim 8 further including a load resistor connected between said output terminal and ground.
 10. An optical comparator comprising:a) a plurality of input channels each including a plurality of independently controllable light sources arranged in an identical pattern; and b) a detector array having a plurality of detectors corresponding and optically coupled to said input channels via a light transfer system, for detecting when all sources corresponding in the corresponding input channel are activated simultaneously and for generating an output signal indicative thereof; wherein each of said input channels corresponds to a digit to be compared and each of said plurality of sources within each of said input channels corresponds to the value of said digit; and wherein each of said detectors includes an output line, the output lines of said detectors being OR'ed together to form a common output line, each of said detectors comprising an opto-electronic AND gate; and wherein said opto-electronic AND gate comprises a plurality of FETs connected in series between a voltage source and an output terminal, and wherein each gate electrode of said plurality of FETs is coupled to a corresponding one of a plurality of input circuits.
 11. An optical comparator as claimed in claim 10 further including a load resistor connected between said output terminal and ground.
 12. An optical comparator as claimed in claim 10, wherein each input circuit comprises a series connection of a diode bias voltage source, a diode, a resistor, and ground, respectively, and wherein said gate electrodes are connected to an anode of said diode associated with said corresponding one of said input circuits. 